/* Generated by Yosys 0.9 (git sha1 1979e0b) */

(* cells_not_processed =  1  *)
(* src = "counter.v:1" *)
module counter(clk, reset, out_nb, out_b, is_one_nb, is_one_b);
  (* src = "counter.v:15" *)
  reg _00_;
  (* src = "counter.v:15" *)
  reg _01_;
  (* src = "counter.v:15" *)
  reg [7:0] _02_;
  (* src = "counter.v:15" *)
  reg [7:0] _03_;
  (* src = "counter.v:15" *)
  reg [7:0] _04_;
  (* src = "counter.v:22" *)
  wire [7:0] _05_;
  (* src = "counter.v:23" *)
  wire [7:0] _06_;
  (* src = "counter.v:25" *)
  wire _07_;
  (* src = "counter.v:26" *)
  wire _08_;
  (* src = "counter.v:13" *)
  reg buff_is_one_b;
  (* src = "counter.v:12" *)
  reg buff_is_one_nb;
  (* src = "counter.v:11" *)
  reg [7:0] buff_out_b;
  (* src = "counter.v:10" *)
  reg [7:0] buff_out_nb;
  (* src = "counter.v:2" *)
  input clk;
  (* src = "counter.v:7" *)
  output is_one_b;
  (* src = "counter.v:6" *)
  output is_one_nb;
  (* src = "counter.v:5" *)
  output [7:0] out_b;
  (* src = "counter.v:4" *)
  output [7:0] out_nb;
  (* src = "counter.v:3" *)
  input reset;
  assign _05_ = buff_out_nb + (* src = "counter.v:22" *) 8'h01;
  assign _06_ = buff_out_b + (* src = "counter.v:23" *) 8'h01;
  assign _07_ = buff_out_nb == (* src = "counter.v:25" *) 8'h01;
  assign _08_ = _06_ == (* src = "counter.v:26" *) 8'h01;
  always @* begin
    _03_ = buff_out_nb;
    _01_ = buff_is_one_nb;
    _00_ = buff_is_one_b;
    _02_ = _04_;
    (* src = "counter.v:16" *)
    casez (reset)
      /* src = "counter.v:16" */
      1'h1:
        begin
          _03_ = 8'h00;
          _04_ = 8'h00;
          _01_ = 1'h0;
          _00_ = 1'h0;
        end
      /* src = "counter.v:21" */
      default:
        begin
          _03_ = _05_;
          _04_ = _06_;
          _01_ = _07_;
          _00_ = _08_;
        end
    endcase
  end
  always @(posedge clk) begin
      buff_out_nb <= _03_;
      buff_out_b <= _02_;
      buff_is_one_nb <= _01_;
      buff_is_one_b <= _00_;
  end
  assign out_nb = buff_out_nb;
  assign out_b = buff_out_b;
  assign is_one_nb = buff_is_one_nb;
  assign is_one_b = buff_is_one_b;
endmodule