Open-source versions of the Digital Computers 1 and 2 labs at University POLITEHNICA of Bucharest, taught by Dan-Ștefan Tudose. The course recommends Xilinx ISE or Vivado, which are closed-source and take tens of gigabytes; these labs run on Icarus Verilog and Make instead, with Yosys for synthesis.
Along the way I cleaned up Verilator’s lint warnings, fixed the use of blocking and nonblocking assignments, removed unsynthesizable initial blocks, and improved the checkers. I also wrote up how the two kinds of assignment differ.
I am forever grateful to our teaching assistant, Ștefan-Dan Ciocîrlan, who supported me far beyond what the job required of him.